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CMX615 digital l ine to pots interface ? 1999 consumer microcircuits limited d/615/4 december 1999 provisional issue features applications pre - programmed tone generators digital line to pots interface fully integrated dtm f encoder subscriber terminal adapters spm generator wireless local loop simple serial control interface computer telephony integ ration ?zero - power? (1a) standby mode telephone/radio patch systems 3.58mhz xtal/clock pair gain systems v23/bell 202 fsk gener ator billing/spm systems digital ringing voltage generator 1.1 brief description the CMX615 is an integrated telecom tone generator and dtmf encode r designed for isdn interfaces, wireless local loop and analogue to digital phone conversion systems. the tone generator covers an extensive range of pre - programmed tones used in analogue phone systems (pots). three outputs are provided: ?ringing signals? , ?in - band tones or fsk data?, and ?12khz/16khz metering pulses?. simple software control facilitates the interface to a wide range of commonly used cs and slics, enabling a comprehensive analogue telephone line presentation. the dtmf encoder generates the appropriate dtmf tones for the pots interface. dtmf tone pairs can be encoded along with each tone singly or with other dual tone signals, such as those used in cidcw systems and ?on hook? signalling systems. other tone standards supported are: fax a nd modem ?answer? and ?originate?, itu (ccitt) ?r1? and ?r2? signals, and sufficient tones for simple melody generation. communication to and from the host controller is performed by a ?c - bus? serial interface, which is compatible with the ?spi? interfac e.
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 2 d/615/4 contents section page 1.1 brief description ................................ ................................ ......................... 1 1.2 block diagram ................................ ................................ ............................ 3 1.3 signal list ................................ ................................ ................................ ... 4 1.4 external components ................................ ................................ ................. 6 1.5 general description ................................ ................................ .................... 7 1.5.1 xtal osc and clock dividers ................................ ....................... 7 1.5.2 uncommitted amplifier ................................ ............................... 7 1.5.3 tone/fsk encoder and tone encoder ................................ ...... 7 1.5.4 spm generator ................................ ................................ .......... 10 1.5.5 transmit operator ................................ ................................ ..... 10 1.5.6 tx uart ................................ ................................ ..................... 10 1.5.7 ?c - bus? interface ................................ ................................ ....... 11 1.5.8 ?c - bus? registers ................................ ................................ ...... 13 1.6 application notes ................................ ................................ ..................... 14 1.6.1 ?telecom tones ................................ ................................ ......... 14 1.6.2 ?c - bus timing ................................ ................................ ........... 17 1.7 performance specification ................................ ................................ ....... 21 1.7.1 electrical performance ................................ .............................. 21 1.7.2 packaging ................................ ................................ .................. 25
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 3 d/615/4 1.2 block diagram figure 1 block diagram
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 4 d/615/4 1.3 signal list CMX615 d4/p3 signal description pin no. name type 1 x taln o/p the output of the on - chip xtal oscillator inverter. 2 xtal/clock i/p the input to the oscillator inverter from the xtal circuit or external clock source. 3 serck i/p the ?c - bus? serial clock input from the host m c. see section 1.5.8 4 comdat a i/p the ?c - bus? serial data input from the host m c. 5 repdata t/s a 3 - state ?c - bus? serial data output to the host m c. this output is high impedance when not sending data to the host m c. 6 csn i/p the ?c - bus? transfer control input provided by the h ost m c. 7 irqn o/p a ?wire - orable? output for connection to a host m c interrupt request input. this output is pulled down to v ss when active and is high impedance when inactive. an external pullup resistor is required. 8 v ss power the negative supply r ail (ground). 9 tonefsk o/p the sinewave output of the tones and fsk signal generators. 10 spm o/p the sinewave output of the spm signal generator.
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 5 d/615/4 CMX615 d4/p3 signal description pin no. name type 11 v bias o/p an internally generated bias voltage of v dd /2, except when the device is in ?zero power? mode when v bias will discharge to v ss . it should be decoupled to v ss by a capacitor mounted close to the device pins. 12 oppin i/p the non - inverting input to the uncommitted amplifier. 13 opn in i/p the inverting input to the uncommitted amplifier. 14 opout o/p the output of the uncommitted amplifier. 15 ring o/p the squarewave output of the ringing signal generator. 16 v dd power the positive supply rail. levels within the device are prop ortional to this voltage. it should be decoupled to v ss by a capacitor mounted close to the device pins. notes: i/p = input o/p = output t/s = 3 - state output it is recommended that the printed circuit board is laid out with a ground plane in th e CMX615 area to provide a low impedance connection between the v ss pin and the v dd and v bias decoupling capacitors.
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 6 d/615/4 1.4 external components figure 2 recommended external components r1 100k w c1, c2 18pf x1 3.579545 mhz c3, c4 1.0f resistors 5%, capacitors 10% unless otherwise stated.
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 7 d/615/4 1.5 general description the CMX615 is a telecom tone generator and dtmf tone encoder. it has separate output ports for the three different classes of signals encoded. these include ringing signal, in - band tones or fsk data at 1200bps and high frequency metering pulses (spm tones). it has a transmit level attenuator for in - band tones or fsk data and an e nvelope control for spm tones. it also has an uncommitted amplifier and uses the industry standard 3.58mhz xtal for its oscillator. these functions are controlled over a ?c - bus? serial c interface, which also carries the transmit fsk data. the CMX615 m ay be powersaved into ?zero - power? mode for minimum power consumption by issuing a ?c - bus? reset command. individual functions may be powersaved by the use of bits 6 and 7 in the setup register. not powersaving the tx powersave (set bit 6 of the setup reg ister to ?1?) will take the tx functions (tone/fsk encoding, dtmf, spm and ringing signal generation) out of powersave. not powersaving the uncommitted amplifier (set bit 7 of the setup register to ?1?) will take the amplifier out of powersave. approxima tely 50ms should be allowed for the tx dc level to settle at v bias before enabling the tx functions (set bit 6 of the mode register to ?1?). 1.5.1 xtal osc and clock dividers frequency and timing ac curacy of the CMX615 is determined by a 3.579545mhz clock present at the xtal/clock pin. this may be generated by the on - chip oscillator inverter using the external components c1, c2 and x1 of figure 2, or may be supplied from an external source to the xta l/clock input. if the clock is supplied from an external source, c1, c2 and x1 should not be fitted. the on - chip oscillator is turned off in the 'zero - power' mode. if the clock is provided by an external source which is not always running, then the 'zer o - power' mode must be set when the clock is not available. failure to observe this rule may cause a rise in the supply current drawn by CMX615. 1.5.2 uncommitted amplifier this amplifier, with suitable ex ternal components, can be used for adjusting the transmit signal level (for the line hybrid). 1.5.3 tone/fsk encoder and tone encoder when bit 5 of the mode register is set to ?1? then these b locks generate fsk signals as determined by bit 0 of the setup register and the tx data bits from the uart block, as shown in the table below: setup register tone/fsk generator fsk signal frequency fsk signal frequency bit 0 ?0? (space) ?1? (mark) 0 v2 3 1200bps fsk 2100hz 1300hz 1 bell 202 1200bps fsk 2200hz 1200hz when bit 5 of the mode register is set to ?0?, these blocks generate single or dual tones from the range shown in the tables on the following pages. bit 6 of the mode register is then us ed to enable or disable the block?s output to the tx signal control, ring and tonefsk outputs. there are four tone fields addressed by bits 0 and 1 of the mode register.
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 8 d/615/4 tone field 0, mode register bit 1 and bit 0 = ?0? and ?0? respectively. tx tones re gister bits 4 - 7 frequency tx tones register bits 0 - 3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = off 0 0 0 0 0 = off 0 0 0 1 252.4 0 0 0 1 * 17.1 0 0 1 0 268.7 0 0 1 0 * 20.5 0 0 1 1 285.3 0 0 1 1 * 24.9 0 1 0 0 315.5 0 1 0 0 * 34.1 0 1 0 1 330.5 0 1 0 1 * 41.0 0 1 1 0 375.2 0 1 1 0 * 51.2 0 1 1 1 404.3 0 1 1 1 - 1 0 0 0 468.0 1 0 0 0 262.9 1 0 0 1 495.8 1 0 0 1 293.6 1 0 1 0 520.6 1 0 1 0 348.2 1 0 1 1 548.0 1 0 1 1 392.6 1 1 0 0 562.8 1 1 0 0 1600 1 1 0 1 578.4 1 1 0 1 1633 1 1 1 0 595.0 1 1 1 0 1827 1 1 1 1 612.5 1 1 1 1 587.2 note: * these outputs are routed to the ring digital output instead of the tonefsk output. any single tone output level at tonefsk output is 0dbm. tone field 1, mode register bit 1 and bit 0 = ?0? a nd ?1? respectively tx tones register bits 4 - 7 frequency tx tones register bits 0 - 3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = off 0 0 0 0 0 = off 0 0 0 1 120 0 0 0 1 330 0 0 1 0 150 0 0 1 0 416 0 0 1 1 154 0 0 1 1 420 0 1 0 0 250 0 1 0 0 425 0 1 0 1 300 0 1 0 1 433 0 1 1 0 350 0 1 1 0 440 0 1 1 1 360 0 1 1 1 450 1 0 0 0 367 1 0 0 0 460 1 0 0 1 375 1 0 0 1 480 1 0 1 0 380 1 0 1 0 500 1 0 1 1 383 1 0 1 1 600 1 1 0 0 400 1 1 0 0 620 1 1 0 1 450 1 1 0 1 720 1 1 1 0 475 1 1 1 0 9 30 1 1 1 1 480 1 1 1 1 -
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 9 d/615/4 tone field 2, mode register bit 1 and bit 0 = ?1? and ?0? respectively tx tones register bits 4 - 7 frequency tx tones register bits 0 - 3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = off 0 0 0 0 0 = off 0 0 0 1 700 0 0 0 1 700 0 0 1 0 900 0 0 1 0 900 0 0 1 1 1100 0 0 1 1 1100 0 1 0 0 1300 0 1 0 0 1300 0 1 0 1 1500 0 1 0 1 1500 0 1 1 0 1700 0 1 1 0 1700 0 1 1 1 - 0 1 1 1 - 1 0 0 0 950 1 0 0 0 2100 1 0 0 1 1400 1 0 0 1 2225 1 0 1 0 1800 1 0 1 0 - 1 0 1 1 2130 1 0 1 1 2750 1 1 0 0 697 1 1 0 0 1209 1 1 0 1 770 1 1 0 1 1336 1 1 1 0 852 1 1 1 0 1477 1 1 1 1 941 1 1 1 1 1633 tone field 3, mode register bit 1 and bit 0 = ?1? and ?1? respectively tx tones register bits 4 - 7 frequency tx tones register bits 0 - 3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = off 0 0 0 0 0 = off 0 0 0 1 540 0 0 0 1 540 0 0 1 0 660 0 0 1 0 660 0 0 1 1 780 0 0 1 1 780 0 1 0 0 900 0 1 0 0 900 0 1 0 1 1020 0 1 0 1 1020 0 1 1 0 1140 0 1 1 0 1140 0 1 1 1 - 0 1 1 1 - 1 0 0 0 1380 1 0 0 0 1380 1 0 0 1 1500 1 0 0 1 1500 1 0 1 0 1620 1 0 1 0 1620 1 0 1 1 1740 1 0 1 1 1740 1 1 0 0 1860 1 1 0 0 1860 1 1 0 1 1980 1 1 0 1 1980 1 1 1 0 - 1 1 1 0 - 1 1 1 1 - 1 1 1 1 -
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 10 d/615/4 1.5.4 spm generator this block operates independently and has its own output pin. it can transmit 12khz or 16khz and is controlled by bit 4 of the setup register. bit 7 of the mode register is used to enable or disable this block. the signal has a rise and fall time each of about 4.5ms. the spm signal rises from the bias level to 0dbm in 16 steps of ? 2db magnitude, and falls from 0dbm to bias level in 16 steps of ? 2db magnitude. 1.5.5 transmit signal control this b lock adjusts the amplitude of the fsk transmit signal output level, the level skew between dtmf tones and the signal routing to the output ports. output signal levels are proportional to v dd . the nominal output signal levels (at 0db attenuation and v dd = 5.0v) are: single tone 0dbm dual tone (per tone) - 3dbm dtmf high frequency tone - 3dbm dtmf low frequency tone - 5dbm fsk signal 0dbm the ring signal is digital: a square wave with amplitude of ? v dd peak to peak. when the ring signal is not select ed, the ring output pin is connected to v ss . the level attenuator provides for level adjustment from 0db to - 14db in - 2db steps. the typical level is determined by bits 2 to 4 of the mode register as shown in the table below: mode register signal level adjustment bit 4 bit 3 bit 2 (db) 0 0 0 0 0 0 1 - 2 0 1 0 - 4 0 1 1 - 6 1 0 0 - 8 1 0 1 - 10 1 1 0 - 12 1 1 1 - 14 1.5.6 tx uart this block connects the c, via the ?c - bus? interface, to the fsk encoder. the bloc k can be programmed to convert transmit data from 8 - bit bytes to asynchronous data characters by adding start and stop bits. the transmit data is then passed to the fsk encoder. data to be transmitted should be loaded by the c into the tx data register when the tx data ready bit (bit 6) of the status register goes high. it will then be treated by the tx uart block in one of two ways, depending on the setting of bit 1 of the setup register: if bit 1 of the setup register is ?0? (tx sync mode) then the 8 bits from the tx data register will be transmitted sequentially at 1200bps, lsb (d0) first. if bit 1 of the setup register is ?1? (tx async mode) then bits will be transmitted as asynchronous data characters at 1200 bps according to the following format:
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 11 d/615/4 one start bit (space) eight data bits (d0 - d7) from the tx data register, with the lsb (d0) transmitted first one stop bit (mark) failure to load the tx data register with a new value when required will result in bit 7 (tx data underflow) of the status r egister being set to ?1?. if the ?tx async? mode of operation is selected then a continuous mark (?1?) signal will be transmitted until a new value is loaded into tx data. if the ?tx sync? mode is selected then the byte already in the tx data register wil l be re - transmitted. figure 3a async mode figure 3b sync mode 1.5.7 ?c - bus? interface this block provides for the transfer of data and control or status information between the CMX615?s internal registe rs and the c over the ?c - bus? serial bus. each transaction consists of a single register address byte sent from the c which may be followed by a single data byte sent from the c to be written into one of the CMX615?s write only registers, or a single by te of data read out from one of the CMX615?s read only registers, as illustrated in figure 4. data sent from the c on the command data (comdata) line is clocked into the CMX615 on the rising edge of the serial clock (serck) input. reply data (repdata) se nt from the CMX615 to the c is valid when the serial clock is high. the interface is compatible with the most common c serial interfaces such as sci, spi and microwire, and may also be easily implemented with general purpose c i/o pins controlled by a s imple software routine. see figure 8 for detailed ?c - bus? timing requirements.
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 12 d/615/4 figure 4 ?c - bus? transactions
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 13 d/615/4 1.5.8 ?c - bus? registers write only registers command data byte (bits 7 - 0) addr. reg ister 7 6 5 4 3 2 1 0 $01 reset n/a n/a n/a n/a n/a n/a n/a n/a $d0 setup uncommitted amplifier: 0 = powersave 1 = not powersave tx powersave: 0 = powersave 1 = not powersave reserved set to 0 spm: 0 = 12khz 1 = 16khz reserved set to 0 reser ved set to 0 fsk mode: 0 = sync 1 = async fsk mode: 0 = v23 1 = bell 202 $d1 mode spm o/p: 0 = disable 1 = enable tone/fsk: 0 = disable 1 = enable tone/fsk: 0 = tone 1 = fsk tx level: (msb) tx level: tx level: (lsb) tone fields: (msb) tone fields : (lsb) $d3 tx data d7 d6 d5 d4 d3 d2 d1 d0 $d4 tx tones d7 d6 d5 d4 d3 d2 d1 d0 read only registers reply data byte (bits 7 - 0) addr. register 7 6 5 4 3 2 1 0 $df status fsk mode: fsk mode: reserved reserved reserved reserved reserved reser ved fsk tx data underflow fsk tx data ready set to 0 set to 0 set to 0 set to 0 set to 0 set to 0 notes: 1. accessing the reset register over the ?c - bus? clears all of the bits in the setup, mode, tx data, tx tones and status registers. this will s et the device into the zero power mode. note that this is a single - byte ?c - bus? transaction consisting solely of the address byte value $01. 2. if any of bits 6 or 7 of the status register is ?1? then the irqn output will be pulled low. 3. reading the status register clears the irqn output. bits 6 and 7 of the status register are cleared on writing to the tx data register.
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 14 d/615/4 1.6 application notes when using the tone/fsk bit (bit 6) of the mode register, eac h tone starts from v bias, and returns to v bias before ending: figure 5 tone starting and stopping when switching between tones in the same column (bits 4 - 7 or bits 0 - 3) of the tx tones register), the transition will be phase continuous. howeve r, switching to the ?off? state will immediately take the output of that tone generator to v bias . figure 6 tone changing tx tones register decodes which do not have a frequency allocated are indicated by a dash ( - ) in the tone field tables. these values should not be used. 1.6.1 ?telecom tones the following tables give the hex codes to be programmed into the particular tone field location for various telecommunications systems applications. the tables ar e not exhaustive, but list the more commonly used tones. ringing signals (f + - 2.5%) field 0 (hz) (hex) off $00 16.7 $01 20 $02 25 $03 35 $04 40 $05 50 $06
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 15 d/615/4 on hook ?cpe alert tones single tone dual tone field 0 field 0 (hz) (h ex) (hz) (hex) 375.2 $60 375.2+1827 $6e 404.3 $70 404.3+1827 7e 468 $80 468+1827 $8e 495.8 $90 495.8+1827 $9e 520.6 $a0 520.6+1827 $ae 548 $b0 548+1827 $be 562.8 $c0 562.8+1827 $ce 578.4 $d0 578.4+1827 $de 1633 $0d nynex (mraa) - am r alert tones (single tone) group a group b field 0 field 0 (hz) (hex) (hz) (hex) 252.4 $10 468 $80 268.7 $20 495.8 $90 285.3 $30 520.6 $a0 315.5 $40 562.8 $c0 330.5 $50 595 $e0 375.2 $60 612.5 $f0 single frequency call progress ton es field 1 (hz) (hex) off $00 120 $10 150 $20 154 $30 250 $40 300 $50 350 $60 400 $c0 425 $04 440 $06 450 $07 480 $09 500 $0a 600 $0b 620 $0c
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 16 d/615/4 dual frequency call progress tones additive mixing m ultiplicative m ixi ng field 1 field 1 (hz) (hex) (hz) (hex) off $00 350+440 $66 400*16.2 $b2 440+480 $f6 400*20 $a3 480+620 $fc 400*25 $94 400+425 $c4 400*33 $85 400+450 $c7 400*40 $76 425+450 $d4 400*50 $67 425+480 $f4 450*25 $e4 120+620 $1c 600*1 20 $fd 150+450 $27 dual tone multi frequency generation field 2 (hz) (hex) off $00 941+1633 $ff 697+1209 $cc 697+1336 $cd 697+1477 $ce 770+1209 $dc 770+1336 $dd 770+1477 $de 852+1209 $ec 852+1336 $ed 852+1477 $ee 941+1336 $fd 941+1209 $fc 941+1477 $fe 697+1633 $cf 770+1633 $df 852+1633 $ef special information tones, fax and modem tones and customer premises alert tones field 2 (hz) (hex) off $00 950 $80 1100 $30 13 00 $40 1400 $90 1800 $a0 2100 $08 2225 $09 2130+2750 $bb
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 17 d/615/4 ccitt ?r1? signalling tones field 2 (hz) (hex) 700+900 $12 700+1100 $13 900+1100 $23 700+1300 $14 900+1300 $24 1100+1300 $34 700+1500 $15 900+1500 $25 1100+1500 $35 13 00+1500 $45 700+1700 $16 900+1700 $26 1100+1700 $36 1300+1700 $46 1500+1700 $56 ccitt ?r2? signalling tones forward mode backward mode field 3 field 3 (hz) (hex) (hz) (hex) off $00 off $00 1380+1500 $89 1140+1020 $65 1380+1620 $ 8a 1140+900 $64 1500+1620 $9a 1020+900 $54 1380+1740 $8b 1140+780 $63 1500+1740 $9b 1020+780 $53 1620+1740 $ab 900+780 $43 1380+1860 $8c 1140+660 $62 1500+1860 $9c 1020+660 $52 1620+1860 $ac 900+660 $42 1740+1860 $bc 780+660 $32 1380+1980 $8d 1140+540 $61 1500+1980 $9d 1020+540 $51 1620+1980 $ad 900+540 $41 1740+1980 $bd 780+540 $31 1860+1980 $cd 660+540 $21 1.6.2 ?c - bus timing the relationship between bytes loaded onto the c - bus and th e transmission of fsk bytes is shown diagrammatically in figures 7a, 7b and 7c. there are many ways in which the c - bus can be used to program a device and three suggestions (one for asynchronous fsk - figure 7a - and two for synchronous fsk - figures 7b and 7c) are shown here, together with typical timings. please note that the c - bus timing is not shown to the same scale as the fsk output (it has been magnified by at least 20 times to make it visible on the same scale).
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 18 d/615/4 figure 7a async mode after gen eral reset
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 19 d/615/4 figure 7b sync mode after general reset
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 20 d/615/4 figure 7c sync mode after general reset (using alternative order of commands)
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 21 d/615/4 1.7 performance specification 1.7.1 electrical performance 1.7.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. unit supply (v dd - v ss ) - 0.3 7.0 v voltage on any pin to v ss - 0.3 v dd + 0.3 v current i nto or out of v dd and v ss pins - 50 +50 ma current into or out of any other pin - 20 +20 ma d4/p3 package min. max. unit total allowable power dissipation at tamb = 25c 800 mw ... derating 13 mw/c storage temperature - 55 +125 c ope rating temperature - 40 +85 c 1.7.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. max. unit supply (v dd - v ss ) 2.7 5.5 v operating temperature - 40 +85 c xtal frequency 1 3.575965 3.5831 25 mhz notes: 1. a xtal frequency of 3.579545mhz 0.1% is required for correct operation.
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 22 d/615/4 1.7.1.3 operating characteristics for the following conditions unless otherwise specified: v dd = 2.7v at tamb = 25c and v dd = 3.0v to 5.5v at tamb = - 40 to +85c, xtal frequency = 3.579545mhz 0.1% 0dbm corresponds to 775mvrms. dc parameters notes min. typ. max. unit i dd zero - power mode 1, 2 - <1.0 - m a opamp only enabled, v dd = 5.0v 1 - 1.5 - ma opamp only en abled, v dd = 3.3v 1 - 0.75 - ma all enabled, v dd = 5.0v 1 - 5.0 7.5 ma all enabled, v dd = 3.3v 1 - 3.0 4.5 ma logic ?1? input level 3 70% - - v dd logic ?0? input level 3 - - 30% v dd logic input leakage current (vin = 0 to v dd ), 3 - 1.0 - +1.0 a (excluding xtal/clock input) output logic ?1? level (i oh = 360a) v dd - 0.4 - - v output logic ?0? level (i ol = 360a) - - 0.4 v irqn o/p ?off state current (v out = v dd ) - - 1.0 a fsk encoder and tx uart notes min. typ. max. unit level at tonefsk pin 4 - 1.0 0.0 1.0 dbm twist (mark level wrt space level) - 2.0 0 +2.0 db tx 1200bits/sec (v23 mode) baud rate (set by uart and xtal frequency) 1194 1200 1206 baud mark (logical 1) frequency 1297 1300 1303 hz space (log ical 0) frequency 2097 2100 2103 hz tx 1200bits/sec (bell 202 mode) baud rate (set by uart and xtal frequency) 1194 1200 1206 baud mark (logical 1) frequency 1197 1200 1203 hz space (logical 0) frequency 2197 2200 2203 hz tonef sk signal level notes min. typ. max. unit level at tonefsk pin for: single tone 4 - 1.0 0 1.0 dbm dual tone (per tone) 4 - 4.0 - 3.0 - 2.0 dbm dtmf high frequency group 4 - 4.0 - 3.0 - 2.0 dbm dtmf low frequency group 4 - 6.0 - 5.0 - 4.0 dbm output im pedance - 10.0 - k w tone frequency resolution - 2.0 - 2.0 hz tone output distortion 5 - 0.8 - % notes: 1. at 25 c, not including any current drawn from the CMX615 pins by external circuitry other than x1, c1 and c2. 2. all logic inputs at v ss except for csn input which is at v dd . 3. excluding xtal/clock pin. 4. at v dd = 5.0v, load resistance greater than 40k w , signal levels are proportional to v dd . 5. frequency above 300hz. 6. spm has a soft rise and fall time of about 4.5ms. the level changes between v bias and 0dbm in 2db steps, 16 steps per rise and fall. when spm is disabled, an extra 4.5ms falling tail end of signal should be taken into consideration.
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 23 d/615/4 spm signal level notes min. typ. max. unit level at sp m pin 4, 6 - 1.5 0 1.0 dbm 4,6,8 - 1.0 0 0.5 dbm tone frequency accuracy - 14.0 - 14.0 hz tone output distortion 5 - 1.2 - % output impedance - 10.0 - k w uncommitted amplifier notes min. typ. max. unit open loop gain (i/p = 1mvrms at 100hz) - 6 0.0 - db unity gain bandwidth - 5.0 - mhz input impedance (at 100hz) 10.0 - - m w output impedance (open loop) - 10.0 - k w power - up timing notes min. typ. max. unit zero - power to reliable signal at opout, ring, spm or tonefsk output pi ns. - 50 - ms xtal/clock input notes min. typ. max. unit 'high' pulse width 7 100 - - ns 'low' pulse width 7 100 - - ns input impedance (at 100hz) - 1.0 - m w gain (i/p = 1mvrms at 100hz) 20.0 - - db notes: 7. timing for an external input to the xtal/clock pin. 8. over the range v dd = 3.0 to 5.5v at tamb = 25c.
digital line to pots interface CMX615 ? 1999 consumer microcircuits limited 24 d/615/4 ?c - bus? timings (see figure 8) notes min. typ. max. unit t cse csn - enable to clock - high time 100 - - ns t csh last clock - high to csn - high time 100 - - ns t loz clock - low to reply output enable time 0.0 - - ns t hiz csn - high to reply output 3 - state time - - 1.0 s t csoff csn - high time between transactions 1.0 - - s t nxt inter - byte time 500 - - ns t ck clock - cycle time 500 - - ns t ch seria l clock - high time 200 - - ns t cl serial clock - low time 200 - - ns t cds command data set - up time 75 - - ns t cdh command data hold time 25 - - ns t rds reply data set - up time 75 - - ns t rdh reply data hold time 0 - - ns note: these timings are for the latest version of the ?c - bus? as embodied in the CMX615, and allow faster transfers than the original ?c - bus? timings given in cml publication d/800/sys/3 july 1994. typical uart timings (see figure 3a and 3b) notes min. typ. max. u nit t fsk (delay through the modulator) - 106 - s t dly (1 bit - period) - 833 - s t drdy (1/4 bit - period) - 208 - s t ufl (3/4 bit - period) - 625 - s figure 8 ?c - bus? timing
digital line to pots interface CMX615 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro - static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. specific testing of all circu it parameters is not necessarily performed. oval park - langford maldon - essex cm9 6wg - england telephone: +44 (0)1621 875500 telefax: +44 (0)1621 875600 e - mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk 1.7.2 packaging figure 9 16 - pin soic (d4) mechanical outline: order as part no. CMX615d4 figure 10 16 - pin dil (p3) mechanical outline: order as part no. CMX615p3

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